An embedded tester core for system-on-chip architectures

Abstract

Automatic test equipment (ATE) capabilities have been realized using a novel embedded tester core (ETC) core designed to test large system-on-chip (SoC) implementations. The proposed ETC core appears as an additional IP core that is embedded in the system-on-chip. It can perform the advanced timing and control testing requirements that are necessary to apply the deterministic test patterns that are generated by core vendors and SoC designers. At-speed test patterns are applied to the core under test (CUT) to detect static and dynamic faults that are difficult and expensive to cover with a conventional external ATE. The ETC core is designed for at-speed testing with minimum area overhead and low power consumption in 0.18 /spl mu/m CMOS technology.