A High-Gain, Low-Noise, +6dBm PA in 90nm CMOS for 60-GHz Radio

Abstract

A 60-GHz power amplifier with 14 dB gain, 5 dB simulated noise figure, and a saturated output power of +6 dBm was fabricated in a 90 nm GP process with a 9-metal digital back end. The amplifier employs two cascode stages and a common-source output stage with inductive degeneration. It has a power-added-efficiency of 6% while consuming 45 mW from a 1.5-V supply. The robustness and repeatability of the small signal and large signal performance were characterized across dies, power supply voltage, and over temperature up to 125degC. The design was also scaled to 85 GHz in 65 nm CMOS with +5 dBm Psat.