Enhancements to the world's fastest CPLD family give designers more flexibility

Abstract

Over the last decade, Altera has maintained its leadership in the PLD market place by keeping in step with the constantly changing demands of users of programmable logic. This is clearly evident in Altera's release of the MAX 7000E family. This family provides fast set-up times for designs which require fast synchronization of input data. For those users who use multi-phase clocking, the family provides two global clocks with programmable polarity control. With the introduction of six output enable control signals, which can be generated from either internal logic or from I/O pins, designs have greater flexibility in interfacing with multiple buses such as those found in microprocessor applications. For designers who need control over the speed of which outputs transition, Altera has added programmable output slew rate control which can be selected on an I/O-pin-by-I/O pin basis. All of these enhancements provide designers greater flexibility to interface with system logic.<>