Compaction of two-level microprograms for a multiprocessor computer

Abstract

An optimizing loader has been designed and developed for two-level microprograms of a multiprocessor computer. In the computer, a microinstruction activates nanoprograms in multiprocessors, specifying nanoprogram start address and the processors to be activated. This scheme allows the loader to utilize the same nanoprogram among several microinstructions, which activate it, and compact the nanoaddress space by nanocode movement. The experimental results show that (i) the nanoprogram sizes are reduced from 17.3 to 31.0 % and (ii) the effect of the reduction is proportional to the number of microinstructions.