Write-back technique for single-ended 7T SRAM cell

Abstract

This paper presents the new Write-Back scheme, which solve the half-select operation problem and faster than conventional Write-Back technique for memory array with seven-transistor (7T) single-ended static random access memory (SE-SRAM) bit cell. Data in the cells are sensitive and flipping can happen, so proposed scheme improves the stability issue for half-selected cells without performance degradation.