Quantum-Corrected Simulation of Complementary Nanowire Tunneling Transistors of 5 nm Gate-Length

Abstract

Using numerical device simulation we investigated in detail the operational behavior of a cylindrical nanowire tunneling transistor (TFET) and the effect of quantum confinement on its characteristics, with a strong focus on the scalability of such devices. Among others, we discuss the potential device improvements by considering alternative materials for the gate-stack and the source region.