{"title":"Design of a multiple-valued VLSI processor for digital control","authors":"Katsuhiko Shimabukuro, M. Kameyama, T. Higuchi","doi":"10.1109/ISMVL.1992.186813","DOIUrl":null,"url":null,"abstract":"A high-performance parallel, multivalued VLSI processor using the radix-2 signed-digit number system is proposed. Multivalued bidirectional current-mode technology is used not only in the high-speed small-sized arithmetic circuits, but also in reducing the number of connections. Compactness and high-speed operation enhance the performance of the processor chip under the chip size limitation. The processor has been developed for real-time digital control, where the performance is evaluated by delay time. A performance estimation using SPICE simulators shows that the delay time of the processor for operations such as matrix multiplication is greatly reduced in comparison to a conventional binary processor.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.1992.186813","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A high-performance parallel, multivalued VLSI processor using the radix-2 signed-digit number system is proposed. Multivalued bidirectional current-mode technology is used not only in the high-speed small-sized arithmetic circuits, but also in reducing the number of connections. Compactness and high-speed operation enhance the performance of the processor chip under the chip size limitation. The processor has been developed for real-time digital control, where the performance is evaluated by delay time. A performance estimation using SPICE simulators shows that the delay time of the processor for operations such as matrix multiplication is greatly reduced in comparison to a conventional binary processor.<>