Parallel efficient implementation of hierarchical algorithms for module placement of large chips

Abstract

The PROUD module placement algorithm mainly uses a hierarchical decomposition technique and the solution of sparse linear systems based on a resistive network analogy. It has been shown that the PROUD algorithm can achieve a comparable design of the placement problems for very large circuits with the best placement algorithm based on simulated annealing, but with several order of magnitude faster. The modified PROUD, namely MPROUD algorithm by perturbing the coefficient matrices performs much faster that the original PROUD algorithm. Due to the instability and unguaranteed convergence of MPROUD algorithm we have proposed a new convergent and numerically stable PROUD, namely Improved PROUD algorithm, denoted as IPROUD with attractive computational costs to solve the module placement problems by making use of the MINRES method based on Lanczos process. In this paper, we subsequently propose parallel versions of the original, modified and improved PROUD algorithms that combine both fine and coarse grain parallelism to obtain another order of magnitude improvement in the runtime without loss of the quality of the layout. Experimental results using Message Passing Interface (MPI) on various multiprocessor systems are reported showing its advantages for a variety of large layout benchmark circuits.