A 55ns CMOS EEPROM

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156661

R. Zeman, Chun Ho, T. Chang

引用次数: 6

Abstract

A 32,768 (4K×8) CMOS EEPROM with a 55ns address access time will be discussed. Access time through the memory array was accomplished by using two memory cells per bit. A differential signal is generated on complementary bit lines to reduce the voltage swing necessary for sensing.

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55ns CMOS EEPROM

一个32,768 (4K×8) CMOS EEPROM与55ns地址访问时间将被讨论。通过存储器阵列的访问时间是通过每比特使用两个存储器单元来完成的。在互补的位线上产生差分信号，以减少感应所需的电压摆幅。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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