An analytical model for BiCMOS logic transient response allowing parameter variations

Abstract

A closed-form analytic model for the transient response of a BiCMOS inverter has been demonstrated which allows the gate delay to be predicted with good accuracy over a wide range of circuit and device parameter values. In addition, the model has been shown to be accurate not only when the bipolar transistors operate in low-level injection, but in high-level injection and saturation as well. Since this is a closed-form model, it allows the user to examine the equations directly to determine how the gate delay depends on circuit and device parameters. Possible applications being pursued at this time by the authors include investigating BiCMOS logic performance at low temperatures as well as examining the consequences of physically separating the bipolar and CMOS components of the BiCMOS driver. This could occur in a hybrid packaging scheme which has CMOS chips placed on active silicon substrates in which the bipolar drivers are fabricated