The CMOS analog multiplier free from mobility reduction

Abstract

In this paper, a CMOS analog multiplier circuit is proposed. It consists of eight voltage subtractors, four voltage sources and a multiplier cell. Its major advantage is its freedom from mobility reduction, so it has low total harmonic distortion (THD). For the proposed multiplier cell, its inputs are applied to the drains of the input cell transistors through the voltage sources. Their gates are fixed to the same bias voltage to remove the effect of mobility reduction. The simulation results show that the THD is less than 0.13% for 0.8 V/sub P-P/ input signal at 2.5 V supply voltage, and that the -3 dB bandwidth is up to 38 MHz.