A 1GHz bandwidth low-pass ΔΣ ADC with 20GHz to 50GHz adjustable sampling rate

A. Hart, S. Voinigescu
{"title":"A 1GHz bandwidth low-pass ΔΣ ADC with 20GHz to 50GHz adjustable sampling rate","authors":"A. Hart, S. Voinigescu","doi":"10.1109/RFIC.2008.4561413","DOIUrl":null,"url":null,"abstract":"This paper presents a wideband continuous-time DeltaSigma-modulator intended for multi-gigabit OFDM receiver applications. Two versions of the circuit were fabricated in a 130-nm SiGe BiCMOS process with 170 GHz fT in order to investigate the effect of finite quantizer gain and delay on dynamic range. The ADC achieves an SNDR of 44.3 dB over a 500 MHz passband and an SNDR of 37.1 dB over a 1 GHz passband while consuming 350 mW from a 2.5 V supply (650 mW including clock distribution).","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Radio Frequency Integrated Circuits Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2008.4561413","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

Abstract

This paper presents a wideband continuous-time DeltaSigma-modulator intended for multi-gigabit OFDM receiver applications. Two versions of the circuit were fabricated in a 130-nm SiGe BiCMOS process with 170 GHz fT in order to investigate the effect of finite quantizer gain and delay on dynamic range. The ADC achieves an SNDR of 44.3 dB over a 500 MHz passband and an SNDR of 37.1 dB over a 1 GHz passband while consuming 350 mW from a 2.5 V supply (650 mW including clock distribution).
1GHz带宽低通ΔΣ ADC, 20GHz至50GHz可调采样率
本文提出了一种适用于多千兆OFDM接收机的宽带连续时间增量调制器。为了研究有限量化器增益和延迟对动态范围的影响,我们在170 GHz fT的130 nm SiGe BiCMOS工艺中制作了两个版本的电路。该ADC在500 MHz通频带上的SNDR为44.3 dB,在1 GHz通频带上的SNDR为37.1 dB,而在2.5 V电源上消耗350 mW(包括时钟分布)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信