Low Noise - Low Power CMOS Readout Systems for Silicon Strip Detectors

Abstract

Two readout systems for silicon strip detectors (128-and 64-channels) have has been developed in CMOS technology. The readout systems have been designed for a readout pitch of 50¿m and 100¿m, respectively. They provide signal amplification, noise filtering, parallel storage, and serial readout and contain a digital contol for analog switching. Switched-capacitor filters are used in all channels for noise reduction by multi-correlated double sampling. Power consumption is controlled by an external reference voltage thus allowing for optimization of speed and noise behavior versus power consumption for individual use in experiments. Power-down mode for further reduction of power dissipation is available without switching off the supply voltages. A high charge amplification (15mV/fC) and a good noise performance (335 ENC + 30 ENC/pF) have been obtained at a very low power consumption of 2mW per channel.