Power Reduction of On-Chip Serial Links

Abstract

On-chip serial links to replace standard buses for global communication have been the subject of a number of recent investigations. The main reason for considering serial links is to reduce routing congestion and design complexity. However, the serialization of parallel data may actually increase the power dissipation due to increased switching activity. This paper describes a new bit ordering technique to reduce switching activity on serial links, assuming that the statistical data of the parallel bus traces are known in advance. The method reduces the switching activity by an average of 40% 50% compared to random bit ordering.