Statistically-aided electronic design environment

Abstract

This work presents SAEDE (Statistically-Aided Electronic Design Environment), a framework targeted to perform advanced statistical analysis within an ASIC design workflow, linking together circuit performance with technological parameters. A driving example, the design of a 10-stage delay line, is conducted. The study goals are two-fold: extract a circuit performance metric, the spread of the stage-delay, and determine its most sensitive BSIM4 transistor parameters. To achieve these goals, two statistical tools, new to ASIC design work-flow, have been used: Skew-Normal inference and BAHSIC feature selection. Consistent results are obtained, relating BSIM4 parameters to circuit performance impossible to grasp by analytical terms.