DaeOk Kim, E. Jung, Hyunho Park, Hosoon Shin, D. Har
{"title":"Implementation of High Performance CAVLC for H.264/AVC Video Codec","authors":"DaeOk Kim, E. Jung, Hyunho Park, Hosoon Shin, D. Har","doi":"10.1109/IWSOC.2006.348257","DOIUrl":null,"url":null,"abstract":"Context-based adaptive variable length coding (CAVLC) is entropy coding for H.264/AVC video codec. Since the CAVLC is highly context-adaptive and of a block-based context formation, high coding efficiency is achieved. However, its high complexity causes various difficulties in full-hardware implementation. This paper presents high performance hardware architecture of CAVLC. The proposed architecture is implemented in a FPGA device, and verified by RTL simulations. The implementation results show that the proposed architecture encodes a 4times4 block per 16 clock cycles, and achieves a real-time processing for 1920times1088 frame size with 30-fps video at 100MHz clock speed","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 6th International Workshop on System on Chip for Real Time Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSOC.2006.348257","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
Context-based adaptive variable length coding (CAVLC) is entropy coding for H.264/AVC video codec. Since the CAVLC is highly context-adaptive and of a block-based context formation, high coding efficiency is achieved. However, its high complexity causes various difficulties in full-hardware implementation. This paper presents high performance hardware architecture of CAVLC. The proposed architecture is implemented in a FPGA device, and verified by RTL simulations. The implementation results show that the proposed architecture encodes a 4times4 block per 16 clock cycles, and achieves a real-time processing for 1920times1088 frame size with 30-fps video at 100MHz clock speed