Sub-10 nm High-k Dielectric SOI-FinFET for HighPerformance Low Power Applications

Abstract

In this work, sub-10 nm high-k dielectric Silicon-on-Insulator (SOI) FinFET has been investigated for high-performance analog applications with a very low power supply. The performance analysis of 9 nm gate length high-k SOI-FinFET has been compared with conventional FinFET. It has been evaluated that the proposed device provides better solutions in terms of better subthreshold slope, lowering of threshold voltage, device efficiency, and higher switching ratio (Ion/Ioff ratio). Thus, the high-k dielectric SOI-FinFET device paves the way for high-performance switching applications.