A 1.8 V fully embedded 10 b 160 MS/s two-step ADC in 0.18 /spl mu/m CMOS

Abstract

A two-step ADC with interleaved fine conversion achieves 9.1 effective bits with a sampling frequency of 160 MHz. The effective resolution exceeds 8.5 bits for signal frequencies up to 66 MHz. The 10 bit converter with on-chip driver and reference measures only 1 mm/sup 2/ in a standard 0.18 /spl mu/m CMOS process and consumes 190 mW from a single 1.8 V supply. The fully embedded design is targeted at SoC-integration.