{"title":"A power-efficient search line driver for 3T-2R non-volatile ternary content addressable memory with power gating and replica cell","authors":"I. Jung, K. Kwon","doi":"10.23919/ELINFOCOM.2018.8330702","DOIUrl":null,"url":null,"abstract":"This paper presents a power efficient search line driver circuit for reducing DC current of 3T-2R non-volatile ternary CAM (nvTCAM) using power gating and replica cell. Although the low resistive non-volatile memory has a short write time, a significant DC current through the resistive cell during the search period limits adoption to nvTCAM application. This DC current can be controlled by power gating circuit and the replica cell that senses the proper triggering point for power gating. This method is proved to save the DC current by 90% at maximum, 24% in average when simulated in 64-bit row array using 180nm CMOS technology.","PeriodicalId":413646,"journal":{"name":"2018 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 International Conference on Electronics, Information, and Communication (ICEIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/ELINFOCOM.2018.8330702","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents a power efficient search line driver circuit for reducing DC current of 3T-2R non-volatile ternary CAM (nvTCAM) using power gating and replica cell. Although the low resistive non-volatile memory has a short write time, a significant DC current through the resistive cell during the search period limits adoption to nvTCAM application. This DC current can be controlled by power gating circuit and the replica cell that senses the proper triggering point for power gating. This method is proved to save the DC current by 90% at maximum, 24% in average when simulated in 64-bit row array using 180nm CMOS technology.