Multi-DSP implementation of a H.264/SVC decoder

Abstract

In this paper, the implementation of a Multi-DSP based video decoder compliant with the H.264/SVC standard (14496-10 Annex G) is presented. An optimized single DSP-based decoder implementation has been splitted in two processes: the frame decoding (entropy decoding and motion compensation) and the deblocking filter. A multi-DSP device has been used to parallelize the execution of the processes. The performance has been measured using H.264/SVC sequences with different configurations.