Analysis of Nonlinearity Reduction by Binary and Unary Switching Schemes in DACs

Abstract

This paper focuses on a performance comparison of switching schemes for unary and binary architectures with each other. Typically, only considerations of monotonicity and routing complexity define the architecture choice. Herewith, different properties in terms of systematic error compensation are not taken into account. Systematic error compensation is achieved with so-called switching schemes. This research presents results of simulation for unary and binary switching schemes. The results show that the performance of binary switching schemes degrades with resolution increase. Therefore, for static nonlinearity improvement, binary switching schemes can be used instead of unary ones only at low resolutions (4–6 bits). In terms of dynamic performance, a binary switching scheme can provide a more compact layout by cost of a little loss in the dynamic range.