An FPGA based simulation acceleration platform for spiking neural networks

Abstract

Today's field-programmable gate array (FPGA) technology offers a large number of IO pins in order to realize a high bandwidth distributed memory architecture. Our acceleration platform, called spiking neural network emulation engine (SEE), makes use of this fact in order to tackle the main bottleneck of memory bandwidth during the simulation of large networks and is capable to treat up to 2/sup 19/ neurons and more than 800 10/sup 6/ synaptic weights. The incorporated neuron state calculation can be reconfigured in order to consider sparse or dense connection schemes. Performance evaluations have revealed that the simulation time scales with the number of adaptive weights. The SEE architecture promises an acceleration by at least factors of 4 to 8 for laterally full-connected networks compared to simulations executed by a stand-alone PC.