Feasibility study on vertical CMOS gates

Abstract

Vertical MOSFETs are a promising approach for ultra short channel length transistors. Theoretically, vertical MOSFETs have small lateral size due to their three-dimensional geometry channel compared to the three-dimensional type of conventional MOSFETs. Thus, vertical transistors are very attractive for high density integrated circuits (ICs). The feasibility study concentrates on the layouts of conventional and vertical CMOS for inverter and two-input NOR gates to validate the theory. In this study, the size of the active area and the overall area for gates designed using both types of transistor were compared and analyzed. Based on the comparison, the size of the active area for the gates designed using both types of transistors were equal. However, the overall area of the gates designed using vertical MOSFETs were larger than that of conventional MOSFETs due to the limitation of interconnection of metal between the transistors. Based on the study, although the channel size can be optimized, due to the interconnection requirement in IC implementation, the overall IC area cannot be minimized.