A 1.2 V 300 μW second-order switched-capacitor Δ∑ modulator using ultra incomplete settling with 73 dB SNDR and 300 kHz BW in 130 nm CMOS

Abstract

This paper presents a Δ∑ modulator (Δ∑M) circuit based on the implementation of discrete time filters using ultra incomplete settling (UIS). This approach allows building a Δ∑M using mostly dynamic elements thus reducing the power dissipation. A prototyped 2nd-order Δ∑M circuit, using this technique, was designed in a 130 nm CMOS technology; the measured results prove the validity of the concept. Measured results show that the Δ∑M achieves a peak SNDR of 72.8 dB, a peak SNR of 73.9 dB and a DR of 78.2 dB for a signal with a bandwidth (BW) of 300 kHz, while dissipating less than 300 μW from a 1.2V power supply voltage, resulting in a FOM of 139.3 fJ/conv.-step. As far as the authors have knowledge, this circuit represents the first prototyped switched-capacitor (SC) circuit based on UIS.