Analysis and design of Network on Chip under high process variation

Abstract

Asynchronous router is proposed as a vigorous design to alleviate the impact of process variation in Network on Chip (NoC). The impact of process variation on the network throughput is evaluated by implementing asynchronous and synchronous network on chip designs. Many Network on Chip topologies are used to evaluate the influence of process variation. Circuit analysis is used to evaluate the impact of process variation on both synchronous and asynchronous designs. The delay, throughput and leakage power variation for different NoC topologies are evaluated with taking into consideration NoC interconnects and clock distribution network under process variation with advanced technology. In advanced technologies, process variation crumbles the performance of routing algorithms. For different traffic patterns, the performance of many routing algorithms is determined. Adaptive routing algorithm should be aware of the process variation. To avert the influence of process variation and congestion for asynchronous NoC design, a novel routing algorithm is presented. Process variation Delay and Congestion aware Routing (PDCR) is proposed as adaptive, low cost and scalable routing algorithm. The performance of different routing algorithms is determined and compared to PDCR with process variation under various traffic patterns. Saturation throughput and average message delay are used to evaluate the different routing algorithms. PDCR achieves high performance as compared to different adaptive routing algorithms under various traffic patterns.