{"title":"WiderFrame: An Automatic Customization Framework for Building CNN Accelerators on FPGAs: Work-in-Progress","authors":"Lei Gong, Chao Wang, Xi Li, Xuehai Zhou","doi":"10.1109/CODESISSS51650.2020.9244024","DOIUrl":null,"url":null,"abstract":"Hardware acceleration based on FPGA has been an important means to improve the computational efficiency of CNNs. However, due to the increasing complexity of the modern CNNs and the diversity of neural computing engines, it is challenging to make full use of FPGAs' customizability for efficient and fast accelerator designs. This paper proposes Wider-Frame, an automatic customization framework for building CNN accelerators on FPGA. Towards fully exploiting the customiz-ability of FPGA for specific computing scenarios, WiderFrame integrates a systematical design space exploration methodology considered with different parallel and data reuse manners among various neural computing engines, a parameterized configurable code template with a set of macro instruction mechanism, for automatically generating the underlying hardware units and the control flow. Evaluation results show that WiderFrame can well support more CNN types, and can improve the performance and the energy efficiency up to 1.25 x and 1.68 x compared with state-of-the-art frameworks.","PeriodicalId":437802,"journal":{"name":"2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CODESISSS51650.2020.9244024","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Hardware acceleration based on FPGA has been an important means to improve the computational efficiency of CNNs. However, due to the increasing complexity of the modern CNNs and the diversity of neural computing engines, it is challenging to make full use of FPGAs' customizability for efficient and fast accelerator designs. This paper proposes Wider-Frame, an automatic customization framework for building CNN accelerators on FPGA. Towards fully exploiting the customiz-ability of FPGA for specific computing scenarios, WiderFrame integrates a systematical design space exploration methodology considered with different parallel and data reuse manners among various neural computing engines, a parameterized configurable code template with a set of macro instruction mechanism, for automatically generating the underlying hardware units and the control flow. Evaluation results show that WiderFrame can well support more CNN types, and can improve the performance and the energy efficiency up to 1.25 x and 1.68 x compared with state-of-the-art frameworks.