Built-in self-testable data path synthesis

Abstract

In this paper, we describe a high-level data path allocation algorithm to facilitate built-in self test. It generates self-testable data path design while maximizing the sharing of modules and test registers. The sharing of modules and test registers enables only a small number of registers is modified for BIST, thereby decreasing the hardware area which is one of the major overheads for BIST technique. In our approach, both module allocation and register allocation are performed incrementally. In each iteration, module allocation is guided by a testability balance technique while register allocation aims at increasing the sharing degrees of registers. With a variety of benchmarks, we demonstrate the advantage of our approach compared with other conventional approaches.