Circuit Partitioning optimization using Parallel refinement algorithm

Abstract

Circuit partitioning is a major step in workload distribution for parallel computing system and CMOS VLSI circuit design. Circuit partitioning involves graph partitioning for effective utilization of available CPU power in case of higher number of cores per processor. It improves the degree of partition and amount of parallelism requirement of the partition. In this paper, we propose a shared memory parallel double way method of refinement of current partitioning which can break the local minima. The proposed method shows superiority in comparison to exiting serial refinement methods and achieves speed up of 1.2× to 24.5×24threads while revealing only .37% higher edge cuts in comparison to serial run.