Pre-Tapeout Design for Yield Application: Design based Diffing, Pattern Analytics and Risk Scoring

Abstract

Integrated Circuit manufacturing complexities have resulted in decreased defect limited and parametric limited yields. In leading-edge technologies, silicon learnings are very limited, especially in the early phase of the technology development. In this work, a novel approach of pre-tapeout and pre-mask making verification is introduced using a design diffing methodology to determine a population of new “foundry-unknown” patterns that were never introduced in previous products, scoring them based on their potential manufacturing risk, and identifying suspected yield detractor patterns.