Gate Stack Optimization Toward Disturb-Free Operation of Ferroelectric HSO based FeFET for NAND Applications

Abstract

The utilization of FeFET technology in NAND based architectures is dependent on the role of pass voltage disturb of pass cells during the readout of selected cells. This disturb effect becomes dependent on the FeFET stack parameters and potential optimization for a disturb free operation. In this paper, the impact of pass voltage on the disturb properties of a standard 10 nm Si-doped hafnium oxide (HSO) based FeFETs in a twin gate NAND string is reported. This shows a rather low margin between the pass voltage and strong disturb of pass cells and suggests FeFET stack optimization. A laminate HSO based FE stack (2 × 10nm) with an optimized interface layer (IL) is proposed in benchmark to the standard one to achieve a higher pass window for disturb free operation of the NAND cells. $\text{A}\sim 2\text{x}$ pass window is obtained on the laminated FeFET stack compared to the standard one without jeopardizing the optimal write conditions of the FeFET. The pass voltage disturb properties of unselected NAND cells is reported with emphasis on the potential of an optimized laminate based stack to reduce the pass disturb effect.