An access timing measurement unit of embedded memory

Abstract

As deep sub-micron techniques evolve, embedded memories are dominating the yield, while the testing and measurement issues are more difficult due to access limitations. To solve the testing problem, BIST circuits are developed for testing the functionality of embedded memory, but not for the AC parameters. Based on the dual-slope principle, a new memory access time measurement unit for embedded memories with separate time-to-voltage and voltage-to-time architecture is proposed in this paper to achieve at-speed measurement with 50 ps resolution, where the measurement error is smaller than one LSB, and the linearity error is 1.19%. In conjunction with the March-based BIST circuit, the chip area is 262/spl times/92 /spl mu/m/sup 2/ under a 0.35 /spl mu/m 2P4M CMOS process.