A 0.47-μW Multi-stage Low Noise Amplifier Employing 0.2-V-supply OTA

Abstract

This paper presents an ultra-low power low-noise amplifier (LNA) for neural applications. The proposed LNA uses a squeezed-inverter amplifier (SQI), powered by a 0.2 V supply, to address the main noise source at the input stage to achieve high power efficiency. The proposed LNA is designed in a 180-nm CMOS process. The post-simulation results show that the LNA achieves an input-referred noise of 0.9 μVrms over a bandwidth of 1 kHz. The proposed architecture consumes a power of only 0.47 μW, with a noise efficiency factor (NEF) of 1.47 and a power efficient factor (PEF) of 0.55 over a frequency bandwidth of 10 kHz. The closed-loop gain of the LNA is about 40 dB with a bandwidth of 200 Hz to 10 kHz.