On-Wafer Power Measurements

Abstract

map of Figure 1, 41 d i e ou t of a poss ib l e 122 d i e had g r e a t e r than 32 dBm o f output power. and the d i e s i t e s with "zeros" are d i e t h a t were DC bad. The d e f i n i t i o n of DC bad was any d i e t h a t d id not p inchoff . For example, a d i e wi th a shor t ed ga te has high d r a i n cu r ren t t h a t remains "s tuck" h igh as V,, i s ramped from zero t o a lower l i m i t such a s -5V. A device with a ga t e vo id (open ga te ) has a d r a i n cu r ren t t h a t a l s o remains h igh as V,, is ramped more.negat ive. with "zeros" then a r e d i e t h a t are DC bad, and t i m e w a s n o t spent on RF t e s t i n g . A wafer with 35% y i e l d the re fo re only has RF t e s t t i m e spent on 35% of the d i e , and the f a s t e r DC "screening" i s spent on 65% of the d i e . Figure 2 shows the average y i e l d of devices measured over the l a s t two yea r s . I f wafers t h a t made i t t o t es t a r e the b a s i s of y i e l d , t he average y i e l d was 23%; i f the wafers t h a t s t a r t e d processing a r e the b a s i s of y i e l d , the average y i e l d was 16%. The da ta of Figure 2 is from 700 devices t h a t w e r e power t e s t e d , and the l a r g e amount o f da t a shows t h a t power measurements a t wafer level a r e poss ib l e . Wafer maps of output power have been obtained ( see Figure 1). On the wafer