TCAD driven drain engineering for hot carrier reduction of 3.3V I/O p-MOSFET

Abstract

We present a TCAD driven hot carrier reduction methodology of 3.3V I/O p-MOSFETs design. The drain structures are successfully optimized in short time by applications of TCAD local models. Considering tradeoffs between hot carrier injection (HCI) and I/sub ON/, HALO/SDE of both core and I/O transistors can be totally optimized for photo-mask reduction.