Real-time fault tolerant full adder using fault localization

Sonal Gupta, Ashish Jasuja, Rahul Shandilya
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引用次数: 5

Abstract

Computer complicacy results in a rise up the tendency to fail. A system needs to be built that will recognize the existence of faults and incorporates techniques to will tolerate these faults without troublesome the normal operation. In this paper, we deal with the self-checking full adder and the self-repairing full adder circuit. A proposed self-checking circuit designed such that it can find transient as well as permanent fault depend on internal process and it is able to detect multiple faults at the same time. On the other hand, at the same time, these multiple faults have been repaired by the self-repairing full adder. Both the proposed circuit area efficient and able to recognize and correct multiple faults. The resulting self-repairing circuit occupied less area as compared to the previous circuit and its offer 100 percent detection and correction of the fault.
基于故障定位的实时容错全加法器
计算机的复杂性导致了故障的增加。需要建立一个能够识别故障存在的系统,并结合能够容忍这些故障而不影响正常操作的技术。本文研究了自检测全加法器和自修复全加法器电路。提出了一种根据内部过程既能发现暂态故障又能发现永久故障的自检电路,并能同时检测多个故障。另一方面,自修复式全加法器同时修复了这些多重故障。所提出的电路不仅面积小,而且能够识别和纠正多个故障。与之前的电路相比,由此产生的自修复电路占用的面积更小,并且可以100%检测和纠正故障。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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