Error recognition and correction enhanced decoding of hybrid codes for memory application

Abstract

As technology scales, Multiple Cell Upsets (MCUs) become more common and affect a larger number of cells. In order to protect memories against MCUs as well as SEUs is to make use of advanced Error detecting and correcting codes that can correct more than one error per word. A sub-group of the low-density parity checks (LDPC) codes, which be-longs to the family of the Majority logic decoding has been recently proposed for memory application and Difference set codes are one example of these codes which contributes for error detection and correction. ML decodable Codes are suitable for memory applications due to their capability to correct a large number of errors. In this paper, the proposed scheme for fault-detection and correction method significantly makes area overhead minimal and to reduce the decoding time through DC codes than the existing technique and it gives promising option for memory applications. HDL implementation and synthesis results are included, showing that the proposed techniques can be efficiently implemented.