A symmetric CMOS inverter using biaxially strained Si nano PMOSFET

Abstract

Typical CMOS inverters suffer from current mismatch of PMOS and NMOS transistors which causes asymmetric behavior of the static CMOS inverter. This mismatch is a result of non-equality of several parameters including mobility and threshold voltage of the PMOSFET and NMOSFET. In this paper we proposed a biaxially strained Si PMOSFET to reduce this mismatch. Also we have studied the parasitic channel in the biaxially strained Si PMOS and proposed a novel approach to eliminate this parasitic channel by increasing SiGe virtual substrate doping. Then the improved device has been used in the CMOS inverter which results in a symmetric output behavior with almost equal tPHL and tPLH of 52 ps and 50 ps, high noise margin (NMH) and low noise margin (NML) of 0.16 V and 0.18 V.