A Single-Chip 25.3–28.0 GHz SiGe BiCMOS PLL with −134 dBc/Hz Phase Noise at 10 MHz Offset and −96 dBc Reference Spurs

Abstract

This paper presents a 25.3–28.0 GHz integer-N PLL in a 90 nm SiGe BiCMOS process. The PLL heavily utilizes SiGe HBTs for high-speed and low-noise operation, featuring −96 dBc reference spurs and −97/−107/−134 dBc/Hz phase noise at 1 kHz / 1 MHz / 10 MHz offset. The PLL has 94 fs integrated jitter at a 26 GHz carrier frequency and draws 850 mW from a 3.3V supply for a jitter-power FOM of −231 dBc. The PLL has lower reference spurs and phase noise at 1 kHz and 10 MHz offsets compared to recently published mmW PLLs, making this PLL well-suited for high dynamic range transceiver applications.