Embedding of Thinned RF Chips and Electrical Redistribution Layer Characterization

Abstract

The demand for flexible electronic packaging technologies enabling reliable flexible high-frequency applications is increasing. Embedding of fully integrated wireless transceivers (mm-wave ICs - MMIC) operating at high frequencies needs to be developed. As part of this, to ensure the required embedding technology and the direct contact technology have a proper performance, it is necessary to perform electrical characterization of the embedded chips. In this paper, 1 × 1 mm2 sized silicon test chips with daisy chains were designed and built on thin 200 μm Si-wafer. Subsequently, test chips were embedded in SMC for electrical tests and, in the future, high frequency characterization. The RDL layer is constructed by means of a semi-additive procedure to connect RDL test pads with the daisy chain consisting of chip-level pads and traces, RDL through vias and traces. Metallization is done by PVD and galvanic plating. Measurements were performed primarily to verify a proper interconnection between the metal lines of the RDL layer and the pads on the embedded chip. The resistance-based characterization shows promising results, indicating the interconnects from the embedded chip to the RDL using Cu pillars to be less sensitive against process uncertainties and better defined compared to flip-chip bonding with Au stud- bumps, verifying the prospect of this novel fabrication technique.