A machine-description table based instruction scheduler for improving pipeline execution parallelism on QHRC RISC system

Abstract

This paper presents a parameterized instruction scheduling algorithm based on machine description table for QHRC RISC system, having a 3-5 stage pipeline structure. It would provide considerable flexibility for instruction scheduling, improving execution efficiency for rapidly upgrading RISC machines. And, using this instruction scheduler as a tool, the effect of several methods for solving instruction interlock problem has been analysed. Finally, a high performance approach combining the hardware feasibility and software effectiveness for solving instruction interlock problem and enhancing pipeline execution parallelism is given.<>