A single-event upset robust, 2.2 GHz to 3.2 GHz, 345 fs jitter PLL with triple-modular redundant phase detector in 65 nm CMOS

Abstract

This paper presents a Single Event Upset (SEU) robust low phase-noise PLL for clock generation in harsh environments like nuclear and space applications. The PLL has been implemented in a 65 nm CMOS technology. A low noise LC-tank oscillator is included with a tuning range from 2.2 GHz to 3.2 GHz. The PLL includes a new phase detector and divider with Triple Modular Redundancy (TMR) to suppress Single Event Effects in ionizing radiation environments. A highly reconfigurable bandwidth from 0.7 MHz to 2 MHz provides optimal reference phase noise filtering. The PLL has been designed and measured to operate in a temperature range from −25 C to 125 C and features a jitter of 345 fs rms with a power consumption of 11.7 mW and is tolerant to 10 % supply variations. Single Event Upset laser tests are performed to verify the triplicated circuit performance.