Hardware Design of the H.264/AVC Variable Block Size Motion Estimation for Real-Time 1080HD Video Encoding

R. Porto, L. Agostini, S. Bampi
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引用次数: 14

Abstract

Amongst the video compression standards, the latest one is the H.264/AVC. This standard reaches the highest compression rates when compared to the previous standards. On the other hand, it has a high computational complexity. This high computational complexity makes it difficult the development of software applications running in a current processor when high definitions videos are considered. Thus, hardware implementations become essential. Addressing the hardware architectures, this work presents the architectural design for the variable block size motion estimation (VBSME) defined in the H.264/AVC standard. This architecture is based on full search motion estimation algorithm and SAD calculation. This architecture is able to produce the 41 motion vectors within a macroblock as specified in the standard. The implementation of this architecture was based on standard cell methodology in 0.18μm CMOS technology. The architecture reached a throughput of 34 1080HD frames per second.
实时1080HD视频编码中H.264/AVC可变块大小运动估计的硬件设计
在视频压缩标准中,最新的是H.264/AVC。与以前的标准相比,该标准达到了最高的压缩率。另一方面,它具有较高的计算复杂度。当考虑高清晰度视频时,这种高计算复杂性使得在当前处理器中运行的软件应用程序的开发变得困难。因此,硬件实现变得至关重要。针对硬件架构,本文提出了H.264/AVC标准中定义的可变块大小运动估计(VBSME)的架构设计。该结构基于全搜索运动估计算法和SAD计算。该体系结构能够在标准中指定的宏块内产生41个运动向量。该架构的实现基于0.18μm CMOS技术的标准单元方法。该架构达到了每秒34个1080HD帧的吞吐量。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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