Double-sided rugged poly Si FIN STC (stacked capacitor cell) technology for high density DRAMs

Abstract

The main issue of the high density DRAM cell is to obtain the sufficient cell capacitance in a small area. Many kinds of capacitor structures, for example, cylindrical(1) or crown(2) type stacked cells have been proposed to solve this problem. However, the storage node height of these cells is so high that the following patterning processes become very difficult. Furthermore, their process steps are essentially complex. In this paper, we propose the double-sided rugged poly Si FIN STC technology, having low aspect storage node without any complex processes. This technology is proved to be applicable to 256Mb DRAMs and beyond. The key technology of this cell is to control the shapes of the rugged poly Si by ion implantation. These shapes are changed by ion implantation with arsenic dose more than 5E15 cm-2. Neighboring grains connected each other. These rugged poly Si shapes don't change during the following ion activation annealing. Using this film as the storage node, the FIN structure with the rugged shape on both the upper and the lower surface are achieved. By the TEM observation, there is no sharp edge of the storage node rugged poly Si surface and no thinning of the ONO dielectric film. In this experiment, these capacitors with 2FINs were fabricated in 1.2x0.6 um2 area (cell size for the 256Mb DRAMs ). The total storage node height has become 300nm. The increase ratio of the effective surface area is calculated from C-V measurement for the rugged FIN STC, the conventional FIN STC and the conventional STC. The effective surface area of the rugged FIN STC is 1.8 times as large as that of the conventional FIN STC, and 3.6 times as large as that of the conventional STC. The calculated cell capacitance of the 256Mb DRAM can reach to 25 fJ?/bit with 4 . 5 ~ 1 thickness ONO film. From the cell capacitance dependence on the frequency, there is no degradation in the high frequency region up to 1MHz. It shows that the sheet resistance of this rugged poly Si film is enough low because each grain is connected to the neighboring grains. There is no degradation in I-V characteristics compared with the conventional FIN STC. In conclusion, 25fFbit cell capacitance can be obtained in STC with 2FINs by using this technology. The total storage node height (300nm) is low enough, and there is no degradation in the C-V or I-V characteristic. We demonstrated this rugged FIN STC is one of the most suitable cell structures for the 256Mb DRAMs and beyond because it doesn't need no complex process steps. The separated-grain poly Si is deposited by LPCVD.