A Coarse Count Error Cancellation System Designed for High-Accuracy TDC

Abstract

Time-to-Digital Converter (TDC) uses a hybrid approach to achieve both long-time interval and high resolution. However, as external input signal is asynchronous with the internal working clock of the TDC, there will be ±1 clock cycle error due to the setup time of the TDC clock, which results in coarse time error, seriously affecting TDC timing accuracy. Aiming at the problem, a coarse count error cancellation system is proposed in this work. An extra delay is added to the input pulse to obtain a delayed pulse, and a double sampling mechanism is realized to simultaneously memorize the count values of both the original input pulse and the delayed one. The error is then obtained by comparison. Implemented in a DE2-115 FPGA development platform and tested with different delay values, the proposed system shows a significant ability to effectively reduce the coarse count error in a TDC timing system.