System level interconnect electrical performance characterization

Abstract

In PC/Server industry, simulation process is usually separated into pre-layout and post-layout phase. The pre-layout simulation focus in finding the solution space or choosing a better topology [1], [2]. For post-layout simulation, extracting 3 or 5 pairs of the channel model and conducting the simulation analysis is widely used. However, it requires a basic understanding of the layout. Otherwise the channel which is extracted may not be the best one to represent the worst scenario in the reality. The system level interconnect electrical performance characterization, which can consider a whole interface or even multiple interfaces, become an efficient way, especially estimating the risk of an out-of-guideline design. In this paper, a process with less human interaction is demonstrated. This method can relief the burden in choosing the representative channel from the layout and allow the designer to focus in improving the layout quality in these problematic areas.