Design of a Reed-Solomon decoder using a digital signal processor (DSP)

Abstract

The design of a Reed-Solomon (RS) decoder using two digital signal processors (DSP) is discussed. The RS code is a (255, 223) block code of 8-bit symbols which is capable of correcting up to 16 symbol errors. Any primitive polynomial of GF(2/sup 8/) and generator polynomial for a systematic code can be used. The algorithm used for computing the error-locator polynomial is an Euclid's algorithm. For high-speed decoding, finite field multiplication is carried out by using log and antilog tables in the DSP. A 275 kb/s maximum data transmission rate and 4000 bits for the decoding delay were obtained by using this decoder.<>