Design of High-Speed Sampling and Adaptive Filtering System

Abstract

Aiming at the high-speed matching controlling problems between adaptive filters implemented by FPGA and the high-speed AD converters, a high-speed sampling and adaptive filtering system was designed out using asynchronous FIFO. The dual channels AD converter AD9238-40 was used as input stage, two asynchronous FIFOs on-chip were used as high-speed buffer memory, and the sampling and adaptive filtering was controlled by FPGA. The high-speed matching controlling of the dual channels AD converter AD9238-40 and the adaptive filter were implemented. At last, the schematic diagram of the hardware system was also given out. The sampling and filtering controller and the asynchronous FIFOs was integrated on a chip, it could not only reduce interfere may caused by high frequency, but also the cost of the system.