A compact FPGA implementation of a bit-serial SIMD cellular processor array

Declan Walsh, Piotr Dudek
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引用次数: 7

Abstract

An FPGA implementation of a fine grain general-purpose SIMD processor array is presented. The processor architecture has a compact processing element which is encapsulated into two configurable logic blocks (CLBs) and is then replicated to form an array. A 32 × 32 processing element array is implemented on a low-cost Xilinx XC5VLX50 FPGA using four-neighbour connectivity with the possibility to scale up using a larger FPGA. The processor array operates at a frequency of 150 MHz and executes a peak of 153.6 GOPS (bit-serial operations). Binary and 8-bit greyscale image processing is performed and demonstrated.
位串行SIMD蜂窝处理器阵列的紧凑FPGA实现
提出了一种细粒度通用SIMD处理器阵列的FPGA实现方法。处理器体系结构有一个紧凑的处理元素,它被封装到两个可配置的逻辑块(clb)中,然后被复制形成一个数组。32 × 32处理元件阵列在低成本Xilinx XC5VLX50 FPGA上实现,使用四邻居连接,可以使用更大的FPGA进行扩展。处理器阵列以150mhz的频率工作,执行153.6 GOPS(位串行操作)的峰值。二进制和8位灰度图像处理的执行和演示。
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