Harmonic cancelation strategies for on-chip sinusoidal signal generation using digital resources

Abstract

Harmonic cancelation strategies have been proposed as a promising solution for the implementation of accurate onchip sinusoidal signal generators while minimizing the required on-chip resources. Harmonic cancelation-based generators can be implemented using digital resources to provide a set of phaseshifted digital square-wave signals and a summing network built with passive or active components for scaling and combining these phase-shifted signals. The practical implementation of the scaling weight ratios for the different phased-shifted signals is a critical aspect of the harmonic cancelation strategy. Indeed, small variations between these weights due to mismatch and process variations will reduce the effectiveness of the technique and increase the magnitude of undesired harmonic components. In this work, different harmonic cancelation strategies are presented and analyzed with the goal of simplifying the onchip implementation of the scaling weights. Statistical behavioral simulations are provided in order to demonstrate the feasibility of the proposed approach.