{"title":"Characterization of the High Frequency Performance of 28-nm UTBB FDSOI MOSFETs as a Function of Backgate Bias","authors":"S. Shopov, S. Voinigescu","doi":"10.1109/CSICS.2014.6978546","DOIUrl":null,"url":null,"abstract":"This paper describes for the first time the high frequency performance characterization of a production 28-nm ultra-thin-body-and-BOX (UTBB) fully-depleted (FD) SOI CMOS technology. The measured g<sub>m</sub>, f<sub>T</sub>, and maximum available gain (MAG) of fully-wired n-channel and p-channel MOSFETs are reported as a function of gate-source, drainsource, back-gate voltages and drain current density. It is shown that the back-gate bias can reduce the V<sub>GS</sub> at which the peak g<sub>m</sub>, peak f<sub>T</sub> and peak MAG occur by up to 400 mV and can flatten the f<sub>T</sub>-V<sub>GS</sub> characteristics, as needed in highly linear amplifiers. The peak g<sub>m</sub>/f<sub>T</sub> values of 1.5mS/μm/298GHz and 0.93mS/μm/194GHz, for n-MOSFETs and p-MOSFETs respectively, match or exceed those of 28-nm LP bulk and 45-nm SOI MOSFETs with identical layout geometry and metal stack wiring.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSICS.2014.6978546","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 18
Abstract
This paper describes for the first time the high frequency performance characterization of a production 28-nm ultra-thin-body-and-BOX (UTBB) fully-depleted (FD) SOI CMOS technology. The measured gm, fT, and maximum available gain (MAG) of fully-wired n-channel and p-channel MOSFETs are reported as a function of gate-source, drainsource, back-gate voltages and drain current density. It is shown that the back-gate bias can reduce the VGS at which the peak gm, peak fT and peak MAG occur by up to 400 mV and can flatten the fT-VGS characteristics, as needed in highly linear amplifiers. The peak gm/fT values of 1.5mS/μm/298GHz and 0.93mS/μm/194GHz, for n-MOSFETs and p-MOSFETs respectively, match or exceed those of 28-nm LP bulk and 45-nm SOI MOSFETs with identical layout geometry and metal stack wiring.